1. Field of the Invention
This invention relates in general to flash memory integrated circuit devices. In particular, this invention relates to split-gate flash memory integrated circuit devices and even more particularly, this invention relates to split-gate flash memory cell with separated and self-aligned tunneling regions.
2. Technical Background
Electrically Erasable and Programmable Read-Only Memory (EEPROM) devices have been widely utilized in a variety of electronic equipment, including microcomputer systems. Conventional EEPROM devices have memory cells which comprise floating-gate transistors. Such devices are able to maintain information written into the memory cells in the absence of a power source for the device, and are further capable of having of the information stored in their memory cells erased. These memory devices, however, suffer from their relatively slow read/write access times, which are typically in the range of 150 to 200 nsec. EEPROM devices capable of operating at faster speeds (with 70 to 80 nsec access times) have been developed in the last several years. For example, Intel Corporation of Santa Clara, Calif., has introduced a series of fast EEPROM devices and refers them generically as "Flash Memories."
One of the problems Flash Memory devices suffer from is a problem of "over-erasure" of the memory cell contents during erasure operations. FIG. 1 depicts the construction of a conventional floating-gate transistor. As can be seen in FIG. 1, the floating-gate transistor comprises a floating gate 10 and a control gate 12, capable of injecting electrons from the drain 16, based on a phenomena known as the Fowler-Nordheim Tunneling Effect, through a tunneling oxide layer 14 into the floating gate 10. The threshold voltage of a floating-gate transistor can be raised by means of such electron injection, and the device is then assumes a first state that reflects the content of the memory cell. On the other hand, during erasure of the memory cell, electrons are expelled from the source 18 through the tunneling oxide layer 14 and out of the floating gate 10 of the transistor. As a result of this electron removal, the threshold voltage is lowered and thus the device then assumes a second memory state.
During the process of memory content erasure, however, to ensure complete removal of the electrons previously injected, the erasure operation is normally sustained for a slightly prolonged time period. There are occasions when such a prolonged erasure operation results in the removal of excess electrons, i.e., more electrons than were previously injected. This results in the formation of electron holes in the floating gate of the device. In severe cases, the floating-gate transistor becomes a depletion transistor, which conducts even in the absence of the application of a control voltage at the control gate 12. This phenomena is known in the art as memory over-erasure.
To overcome the above described memory over-erasure problem of conventional EEPROM devices, a split-gate EEPROM device was proposed. FIG. 2a schematically shows such a split-gate device. The memory device comprises a floating-gate transistor, which similarly includes a floating gate 20 and a control gate 22, as is in the case of the floating-gate transistor of FIG. 1. However, the floating gate 20 only covers a portion of the channel region and the rest of the channel region is directly controlled by the control gate 22. This split-gate-based memory cell is equivalent to a series connected floating-gate transistor 33 and an enhanced isolation transistor 35, as is schematically represented in FIG. 2b. The principal advantage of such this configuration is obvious: the isolation transistor 35 is free from influence of the state of the floating gate 20 and remains in its off state, even if the floating-gate transistor 33 is subjected to the phenomena of over-erasure and therefore is in a conductive state. The memory cell can thus maintain its correct state, which reflects the correct state of the memory contents, in spite of over-erasure the problem.
However, the greatest drawback of such split-gate design is the fact that a reduced number of program/erase cycles are allowed. This reduction is due to the fact that the floating gate 20 of this split-gate memory cell configuration is only provided near the drain region 26, which results in different mechanisms occurring for the programming and erasing operations of the device. Electron passage must be via a sequence of drain 26 and through tunneling oxide layer 24, and the resulting reduction of allowable program/erase cycles renders the device suitable only for those applications requiring a relatively few number of program/erase cycles during the entire life span of the device.